Semiconductor device and manufacturing method of semiconductor device

ABSTRACT

A semiconductor device includes a memory transistor including a first side wall insulating film and a second side wall insulating film disposed on the outside; a high-voltage transistor including a third side wall insulating film having the same composition as that of the first side wall insulating film, and a fourth side wall insulating film having the same composition as that of the second side wall insulating film, the fourth side wall insulating film being disposed on the outside; and a low-voltage transistor including a fifth side wall insulating film having the same composition as that of the second and fourth side wall insulating films. The memory transistor, the high-voltage transistor, and the low-voltage transistor are disposed on the same substrate. A total side wall spacer width of the low-voltage transistor is smaller than that of the high-voltage transistor by a thickness corresponding to the third side wall insulating film.

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application is based upon and claims the benefit of priorityunder 35 USC 120 and 365(c) of PCT application JP2007/064998 filed inJapan on Jul. 31, 2007, the entire contents of which are incorporatedherein by reference.

FIELD

The embodiments discussed herein are related to a semiconductor deviceand a manufacturing method of the semiconductor device.

BACKGROUND

In recent years, a semiconductor device, in which a nonvolatile memorycell array and a logic circuit for operating at high-speed are mountedon the same chip, have been in practical use. The logic circuit forperforming high-speed processing is applied to, for example, a CPU or aROM, and is operated at a low voltage to increase the carrier mobility.Meanwhile, a transistor used as the storage for the nonvolatile memoryand a transistor used for selecting memory cells are constituted by highvoltage transistors. Furthermore, analog circuits such as the amplifyingcircuit, the transmission circuit, and the power source circuit are alsoconstituted by high voltage transistors.

The following problem arises when a side wall (hereinafter, simplyreferred to as “side wall” or “SW”) spacer of a low voltage transistorand a side wall (SW) of a high voltage transistor are fabricatedsubstantially simultaneously in a single process by the same procedure.As illustrated in FIG. 1, a low voltage transistor LVTr is miniaturizedfor the purpose of implementing high-speed switching operations. If aside wall 110 of the high voltage transistor HVTr has the same width asthe side wall (SW) of the low voltage transistor LVTr, a length d in thehigh voltage transistor HVTr is reduced. Specifically, the length d isthe length between the leading edge of a source/drain extension 106,which is a low-concentration diffusion layer, and the leading edge of asource/drain 108, which is a high-concentration diffusion layer. As aresult, the concentration profile becomes steep near the junction on thedrain side, and the generation efficiency of impact ionization isenhanced. Accordingly, as illustrated in FIG. 2, the junction withstandvoltage and the snapback withstand voltage on the drain side aredecreased.

Impact ionization is a phenomenon in which the gate current and thesource/drain current rapidly increase when an electron is accelerated toa high-energy state by a high electrical field and collides with anelectron in a valence band, and an electron-hole pair is formed. Asillustrated in FIG. 2, when the breakdown voltage of the high voltagetransistor HVTr, which is the standard voltage, is greater than or equalto 10 V, the voltage BVds at which snapback occurs (breakdown voltagebetween source and drain) decreases to less than 10 V, due to the narrowSW width. As illustrated in the example of FIG. 1, the side wall 110 inboth the high voltage transistor HVTr and the low voltage transistorLVTr has a two-layered structure including an oxide film 110A and anitride film 110B. The same problem as described above arises when theside wall 110 has a single-layered structure or a three-layeredstructure, as long as the side walls on the high-voltage operation sideand the low-voltage operation side have the same structure.

In order to solve the above problem, a technology as illustrated in FIG.3 has been proposed. Specifically, the side walls of a memory transistorand a high voltage transistor HVTr have the same structure. These sidewalls have a larger width than that of the side wall of the low voltagetransistor LVTr (see, for example, patent document 1).

In patent document 1, three types of transistors are disposed atpredetermined positions on a silicon substrate 201. On each of thepoly-gate electrodes 205, 215, and 225 of the transistors, a first oxidefilm 210A, a first nitride film 210B, and a second oxide film 220 aresequentially formed by a low-temperature, low-pressure CVD method. Thetemperatures at which the first oxide film 210A, the first nitride film210B, and the second oxide film 220 are formed (film formingtemperature) are 640° C., 700° C., and 640° C., respectively.Subsequently, only in the low voltage transistor LVTr, the second oxidefilm 220 is removed by a wet etching method. Then, a dry etching methodis performed to etch back the SW films of all of the transistors.Accordingly, the memory transistor and the high voltage transistor HVTrhave a two-layered structure including a first side wall 210 and asecond side wall (second oxide film) 220 positioned outside the firstside wall 210, while the low voltage transistor LVTr has only the firstside wall 210. Forming the three types of SW films at a low temperatureprevents degrading (Ids degradation) of the electric properties of thelow voltage transistor LVTr.

In the example illustrated in FIG. 3, the memory transistor is afloating gate type transistor including a tunnel insulating film 202, afloating gate 203, an ONO (oxide-nitride-oxide) film 204, and a controlgate 205. The high voltage transistor HVTr and the low voltagetransistor LVTr are field-effect transistors including gate electrodes215 and 225 that are provided on the same substrate 201 via gateinsulating films 212 and 222, respectively.

Patent document 1: Japanese Laid-Open Patent Application No. 2004-349680

In patent document 1, the SW width of the miniaturized low voltagetransistor LVTr is smaller than that of the memory transistor or thehigh voltage transistor HVTr, and therefore the performance of the lowvoltage transistor LVTr is improved. However, when the three types oftransistors are formed at once, all of the first side walls 210 incontact with side walls of the gate electrodes (including laminated gateelectrode) is formed at a low temperature, in accordance with thetemperature for forming the low voltage transistor LVTr. Accordingly, itis difficult to ensure data saving properties.

SUMMARY

According to an aspect of the invention, a semiconductor device includesa first transistor including a first gate side wall insulating film anda second gate side wall insulating film disposed outside of the firstgate side wall insulating film; a second transistor including a thirdgate side wall insulating film that has the same composition as that ofthe first gate side wall insulating film, and a fourth gate side wallinsulating film that has the same composition as that of the second gateside wall insulating film, the fourth gate side wall insulating filmbeing disposed outside of the third gate side wall insulating film; anda third transistor including a fifth gate side wall insulating film thathas the same composition as that of the second gate side wall insulatingfilm and the fourth gate side wall insulating film. A total side wallspacer width of the third operation transistor is smaller than that ofthe second transistor by a thickness corresponding to the third gateside wall insulating film.

Additional objects and advantages of the embodiments will be set forthin part in the description which follows, and in part will be obviousfrom the description, or may be learned by practice of the invention.The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe appended claims. It is to be understood that both the foregoinggeneral description and the following detailed description are exemplaryand explanatory and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is for describing problems of a conventional high voltagetransistor HVTr;

FIG. 2 is a graph indicating problems of the conventional high voltagetransistor HVTr;

FIG. 3 is for describing a known method for solving the problemsillustrated in FIGS. 1 and 2;

FIG. 4 illustrates the basic structure of a semiconductor deviceaccording to an embodiment of the present invention;

FIG. 5 illustrates configurations of the high voltage transistor HVTrand the low voltage transistor LVTr illustrated according to anembodiment of the present invention;

FIGS. 6A through 6Q illustrate a manufacturing process of asemiconductor device according to an embodiment of the presentinvention;

FIG. 7 is a graph illustrating effects of a semiconductor deviceaccording to an embodiment of the present invention; and

FIGS. 8A through 8D illustrate a manufacturing process of asemiconductor device according to another embodiment of the presentinvention.

DESCRIPTION OF EMBODIMENTS

Preferred embodiments of the present invention will be explained withreference to accompanying drawings.

FIG. 4 is a schematic cross-sectional view of a configuration example ofa semiconductor device 40 according to an embodiment of the presentinvention. The semiconductor device 40 includes a memory transistor, ahigh voltage (high-voltage operation) transistor HVTr, and a low voltage(low-voltage operation) transistor LVTr.

The memory transistor is a transistor (Flash) that is used in, forexample, a nonvolatile flash memory. The transistor (Flash) includes alaminated gate electrode (flash gate) 45 formed by sequentiallylaminating a floating gate 3, an ONO (oxide-nitride-oxide) film 4, and acontrol gate 5, on a silicon substrate 1 via a tunnel insulating film 2.A first side wall (gate side wall insulating film) 10M is provided onthe side wall of the flash gate 45, and a second side wall (gate sidewall insulating film) 20M is provided outside the first side wall 10M.The first side wall 10M has a film structure having a higher densitythan the second side wall 20M. The first side wall 10M is constitutedby, for example, a thermally-oxidized film 10A′ and a CVD-nitride film10B. The second side wall 20M is constituted by, for example, a CVD-TEOS(tetra-ethyl ortho-silicate) film 20A and a low-temperature CVD-nitridefilm 20B. The first side wall 10M and the second side wall 20Mconstitute a side wall spacer of the flash gate 45.

The high voltage transistor HVTr has the same side wall structure asthat of the memory transistor (Flash). On the side wall of a gateelectrode 15 disposed on the silicon substrate 1 via a gate insulatingfilm 12, there is provided a first side wall 10H having a high density.A second side wall 20H is provided outside the first side wall 10H. Thefirst side wall 10H is constituted by a thermally-oxidized film 10A″ andthe CVD-nitride film 10B. The second side wall 20H is constituted by theCVD-TEOS film 20A and the low-temperature CVD-nitride film 20B. Thefirst side wall 10H and the second side wall 20H constitute a gate sidewall spacer of the high voltage transistor HVTr.

In the low voltage transistor LVTr, a second side wall 20L, which hasthe same thickness and the same composition as that of the second sidewall of the memory transistor (Flash) and the high voltage transistorHVTr, is provided on the side wall of a gate electrode 25. In thisexample, the gate side wall spacer of the low voltage transistor LVTr isconstituted only by the second side wall 20L. The gate side wall spacerof the low voltage transistor LVTr has a spacer width that is smallerthan that of the gate side wall spacer of the high voltage transistorHVTr by a thickness of the first side wall 10H.

The semiconductor device 40 is described below in detail. First, theflash gate 45 of the memory transistor (Flash) and the gate electrode 15of the high voltage transistor HVTr are formed. Then, thethermally-oxidized films 10A′ and 10A″ and the CVD-nitride films 10B areformed at a high temperature (for example, 880° C. through 1000° C. and780° C. through 900° C., respectively), thereby forming insulating filmshaving a high density. Then, a dry etching method is performed to etchback the insulating films. Accordingly, the inner SW (first side walls)10M and 10H having good memory data saving properties and highmechanical strength are formed substantially simultaneously in a singleprocess. Then, the gate electrode 25 of the low voltage transistor LVTris formed. Then, on all three types of transistors, the CVD-TEOS film20A and the low-temperature CVD-nitride film 20B are formed attemperatures of 600° C. through 670° C. and 630° C. through 700° C.,respectively. Then, these films are etched back, so that the second sidewalls 20M, 20H, and 20L are formed substantially simultaneously in asingle process. Accordingly, the electric properties of the miniaturizedlow voltage transistor LVTr are maintained, while the memory transistor(Flash) and the high voltage transistor HVTr have side walls with asufficient width.

FIG. 5 illustrates configurations of the high voltage transistor HVTrand the low voltage transistor LVTr illustrated in FIG. 4. The highvoltage transistor HVTr has a large spacer width (SW width), whichcorresponds to the total width of the first side wall 10H on the inside(flash SW width) and the second side wall 20H on the outside (logic SWwidth). The position of the leading edge of a source/drain impuritydiffused layer 34, which is formed in a well 31 in the silicon substrate1, is spaced away from the leading edge of a source/drain extension 33by a length d (from the position immediately below the channel). Thus,the impurity density of the source/drain extension 33 has a moderatetilt in the horizontal direction. Accordingly, generation of impact ionsis reduced, and the junction withstand voltage and the snapbackwithstand voltage on the drain side are increased.

Meanwhile, the low voltage transistor LVTr has a small spacer width (SWwidth) corresponding to the width of the second side wall 20L, for thepurpose of miniaturization. The density profile of a source/drainimpurity diffused layer 38 with respect to a source/drain extension 37formed in a well 32 is determined by the SW width of the second sidewall 20L, and therefore the low voltage transistor LVTr operates inaccordance with the miniaturized structure.

FIGS. 6A through 6Q illustrate a manufacturing process of thesemiconductor device 40 illustrated in FIG. 4. First, as illustrated inFIG. 6A, resist 41 is applied on the whole surface of the siliconsubstrate 1 on which a device isolation region (not illustrated) and awell region of a predetermined conductivity type (not illustrated) areformed. Then, only a region corresponding to the high voltage transistorHVTr is exposed, and channel ions for the high voltage transistor HVTrare implanted. For example, the implanting conditions are that boron (B)is implanted by 200 keV, 2E13 cm⁻² in the case of NMOS, and phosphorus(P) is implanted by 400 keV, 8E12 cm⁻² in the case of PMOS.

Next, as illustrated in FIG. 6B, the resist 41 is removed, and newresist 42 is applied. Only a region corresponding to the memorytransistor (Flash) is exposed, and channel ions for the memorytransistor (Flash) are implanted. For example, boron (B) is implanted by50 keV, 7E13 cm⁻².

Next, as illustrated in FIG. 6C, the resist 42 is removed, and athermally-oxidized film (SiO2 film) 2 having a thickness of 10 nm isformed on the whole surface of the semiconductor device 40 at 1100° C.The thermally-oxidized film becomes the tunnel insulating film 2 of thememory transistor (Flash).

Next, as illustrated in FIG. 6D, a doped polysilicon film having athickness of 100 nm is formed on the tunnel insulating film 2. The filmis formed at a temperature of, for example, 540° C., and is doped inphosphorus (P) ions at a doping density of 5E19 cm³. By performing aphotolithography method and an etching method, the polysilicon film andthe thermally-oxidized film 2 are patterned into a predetermined shape,and the floating gate 3 of the memory transistor (Flash) is formed.

Next, as illustrated in FIG. 6E, the ONO film 4 is formed on the wholesurface of the semiconductor device 40. For example, the ONO film 4 isformed by forming a silicon oxide film (SiO2) 41 having a thickness of 6nm by a CVD method, and then forming a silicon nitride film (SiN) 42having a thickness of 8 nm on the silicon oxide film (SiO2) 41 by a CVDmethod, and then forming a silicon oxide film (SiO2) 43 having athickness of 250 nm on the silicon nitride film (SiN) 42.

Next, as illustrated in FIG. 6F, resist 46 is formed on the wholesurface of the semiconductor device 40. Then, only a regioncorresponding to the low voltage transistor LVTr is exposed, and channelions for the low voltage transistor LVTr are implanted through the ONOfilm 4. For example, the implanting conditions are that boron (B) isimplanted by 10 keV, 4E13 cm⁻² in the case of NMOS, and arsenic (As) isimplanted by 100 keV, 2E13 cm⁻² in the case of PMOS.

Next, as illustrated in FIG. 6G, the region corresponding to the memorytransistor (Flash) is covered by a mask 48, and the ONO film 4 isremoved from the regions corresponding to the high voltage transistorHVTr and the low voltage transistor LVTr by a dry etching method.

Next, as illustrated in FIG. 6H, in both the high voltage transistorHVTr and the low voltage transistor LVTr, a wet oxide method isperformed to form the gate oxidized films 12 and 22, respectively. Inthe region corresponding to the high voltage transistor HVTr, the gateoxidized film 12 having a thickness of 16 nm is formed at an oxidizingtemperature of 900° C. In the region corresponding to the low voltagetransistor LVTr, the gate oxidized film 22 having a thickness of 2 nm isformed at an oxidizing temperature of 900° C. The gate oxidized films 12and 22 become the gate insulating films 12 and 22, respectively.

Next, as illustrated in FIG. 6I, a polysilicon film 51 having athickness of 110 nm is formed on the whole surface of the semiconductordevice 40. The regions corresponding to the high voltage transistor HVTrand the low voltage transistor LVTr are covered by a mask 52. Thepolysilicon film 51 and the ONO film 4 in the Flash region are processedby performing a photolithography method and an etching method, so as toform the flash gate (laminated gate electrode) 45 including the controlgate 5, the ONO film 4 serving as an interlayer capacitance film, andthe floating gate 3.

Next, as illustrated in FIG. 6J, a screen oxidized film 49 used whenimplanting ions is formed on the side walls of the flash gate 45. Thescreen oxidized film (flash gate side wall oxidized film) 49 is formedby thermal oxidation at, for example, 900° C., to have a thickness of 5nm through 11 nm.

Next, as illustrated in FIG. 6K, the regions corresponding to the highvoltage transistor HVTr and the low voltage transistor LVTr are coveredby a mask 54. Ions for the source/drain extension are implanted into theflash region. For example, the ion implantation is performed by implantenergy of 40 keV and with a dose amount of 2E14 cm⁻².

Next, as illustrated in FIG. 6L, the polysilicon film 51 in the highvoltage transistor HVTr region is processed to form the gate electrode15. Then, a mask 55 is formed such that only the high voltage transistorHVTr is exposed, and ions for the source/drain extension of the highvoltage transistor HVTr are implanted. For example, the implantingconditions are that phosphorus (P) is implanted by 50 keV, 4E13 cm⁻² inthe case of NMOS, and boron fluoride (BF2) is implanted by 50 keV, 4E13cm⁻² in the case of PMOS.

Next, as illustrated in FIG. 6M, the first side walls 10M and 10H areformed on the side walls of the flash gate 45 and the gate electrode 15of the high voltage transistor HVTr, respectively. Specifically, themask 55 is removed, and thermal oxidation is performed at 900° C. toform a silicon oxide film having a thickness of 10 nm on the side wallsof the flash gate 45 and the gate electrode 15 of the high voltagetransistor HVTr. The oxidized film 49 is already formed on the sidewalls of the flash gate 45, and therefore, after the thermal oxidationprocedure, the thermally-oxidized film 10A′ formed on the side walls ofthe flash gate 45 has a larger thickness than that of thethermally-oxidized film 10A″ formed on the side walls of the gateelectrode 15 of the high voltage transistor HVTr. Then, the CVD-nitride(SiN) film 10B having a thickness of 73 nm is formed on the wholesurfaces of the thermally-oxidized films 10A′ and 10A″ at a temperatureof 800° C., and the CVD-nitride (SiN) film 10B is etched back.Accordingly, first side walls 10M and 10H having a high density areformed on side walls of the flash gate 45 and the gate electrode 15 ofthe high voltage transistor HVTr, respectively. The first side walls 10Mand 10H having a high density that are formed at a high temperature areeffective in terms of improving the retention of the memory transistor(Flash).

Next, as illustrated in FIG. 6N, a mask 56 is formed such that only theregion corresponding to the low voltage transistor LVTr is exposed, andthe polysilicon film 51 is processed, thereby forming the gate electrode25 of the low voltage transistor LVTr.

Next, as illustrated in FIG. 6O, the gate electrode 25 is used as a maskfor implanting the ions for the source/drain extension of the lowvoltage transistor LVTr. For example, the implanting conditions are thatarsenic (As) is implanted by 4 keV, 1E15 cm⁻² in the case of NMOS, andboron (B) is implanted by 0.4 keV, 8E14 cm⁻² in the case of PMOS.

Next, as illustrated in FIG. 6P, the mask 56 is removed, and the secondside walls 20M, 20H, and 20L are formed substantially simultaneously ina single process on the memory transistor (Flash), the high voltagetransistor HVTr, and the low voltage transistor LVTr. The second sidewalls 20M, 20H, and 20L are collectively referred to as the “second sidewall 20”. The second side wall 20 is formed by forming the CVD-TEOS film20A having a thickness of 30 nm at a temperature of 650° C., and thenforming the low-temperature CVD-nitride film 20B having a thickness of60 nm at a temperature of 680° C. In this example, the total thicknessof the second side wall 20 is 90 nm.

In this state, in the memory transistor (Flash) and the high voltagetransistor HVTr, the second side wall 20M and the second side wall 20Hthat have been formed at low temperatures are respectively positioned onthe outside of the first side wall 10M having a high density and thefirst side wall 10H having a high density that have been formed at hightemperatures. Thus, the widths of the side walls are sufficient formaintaining an appropriate concentration profile of the source/drainextension region. Meanwhile, in the low voltage transistor LVTr, thesecond side wall 20L is formed at a low temperature, and therefore theimpurities for the source/drain extension that have been implanted inthe previous procedure may be prevented from diffusing.

Lastly, as illustrated in FIG. 6Q, ions for the source/drain areimplanted to the memory transistor (Flash), the high voltage transistorHVTr, and the low voltage transistor LVTr. Phosphorus (P) is implantedby 7 keV, 9E15 cm⁻² in the case of NMOS, and boron (B) is implanted by 5keV, 5E15 cm⁻² in the case of PMOS. By implanting the ions in thismanner, a side wall structure with an appropriate configuration and sizeis formed for the three types of transistors, as illustrated in FIG. 4.

FIG. 7 is a graph illustrating the snapback improvement effects of thehigh voltage transistor HVTr according to the semiconductor device ofthe present embodiment. The horizontal axis represents the gate voltageVg (V), the vertical axis represents the insulating withstand voltage BV(V) between the source and drain, the properties of a conventional highvoltage transistor HVTr having a small SW width illustrated in FIG. 1are plotted by rhomboids, and the properties of the high voltagetransistor HVTr having the side wall structure according to theembodiment illustrated in FIGS. 4 and 5 are plotted by squares. When theapplied gate voltage is 2V, the insulating withstand voltage isincreased by greater than or equal to 2.5 V, and when the applied gatevoltage is 4V, the insulating withstand voltage is increased by greaterthan or equal to 3 V.

Furthermore, in the side wall structure according to the presentembodiment, the first side wall 10 on the inside is a film having a highdensity that is formed at a high temperature, and is therefore effectivein terms of improving the retention of the memory transistor (Flash).

FIGS. 8A through 8D illustrate a manufacturing process of a modificationof an embodiment of the present invention. FIG. 8A illustrates the stepperformed after the step illustrated in FIG. 6I. The steps performedbefore the step of FIG. 8A are the same as those illustrated in FIGS. 6Athrough 6I. In the modification, before implanting the ions forsource/drain extension in the memory transistor (Flash), the ions forsource/drain extension are implanted in the high voltage transistorHVTr.

The mask 52 is removed after processing the flash gate 45, and the stepillustrated in FIG. 8A, a mask 72 is formed such that only the regioncorresponding to the high voltage transistor HVTr is exposed, and anetching process is performed on the polysilicon film 51 to form the gateelectrode 15 of the high voltage transistor HVTr.

Next, as illustrated in FIG. 8B, the gate electrode 15 is used as a maskto implant ions for source/drain extension in the high voltagetransistor HVTr. Phosphorus (P) is implanted by 50 keV, 4E13 cm⁻² in thecase of NMOS, and boron fluoride (BF2) is implanted by 50 keV, 4E13 cm⁻²in the case of PMOS.

Next, as illustrated in FIG. 8C, the mask 72 is removed, and theoxidized films 49 having a thickness of 11 nm are formed on the sidewalls of the flash gate 45 and the gate electrode 15 of the high voltagetransistor HVTr, at a temperature of 900° C. In this modification, thethermal oxidized films 49 are formed substantially simultaneously in asingle process on the side walls of the flash gate 45 and the gateelectrode 15 of the high voltage transistor HVTr, and therefore thefinal thickness of the first side wall is the same for the memorytransistor (Flash) and the high voltage transistor HVTr.

Next, as illustrated in FIG. 8D, a mask 74 is formed such that only theregion corresponding to the memory transistor (Flash) is exposed, andions for the source/drain extension of the memory transistor (Flash) areimplanted. The implanting conditions are that arsenic (As) is implantedby 40 keV, 2E14 cm⁻². Subsequently, the mask 74 is removed, and theprocess returns to the step illustrated in FIG. 6M, where the first sidewalls 10M and 10H are formed substantially simultaneously in a singleprocess on the memory transistor (Flash) and the high voltage transistorHVTr, respectively. Specifically, thermally-oxidized films having athickness of approximately 10 nm are formed on the thermal oxidizedfilms 49 at 900° C., thereby forming the silicon oxide films 10A. Then,the CVD-nitride films 10B having a thickness of 73 nm are formed at 800°C. Then, the CVD-nitride films 10B are etched back, so that the firstside walls 10M and 10H are formed on the side walls of the flash gate 45and the gate electrode 15 of the high voltage transistor HVTr,respectively. The difference between FIG. 8D and FIG. 6M is that in FIG.8D, the thickness of the thermally-oxidized films 10A on the inside ofthe first side walls 10M and 10H is the same for the memory transistor(Flash) and the high voltage transistor HVTr. Thus, not only do thethermally-oxidized films 10A of the memory transistor (Flash) and thehigh voltage transistor HVTr have the same composition, but they alsohave the same thickness. The subsequent steps are the same as thoseillustrated in FIGS. 6N through 6Q.

By performing this method, the first side walls 10M and 10H that arerespectively formed adjacent to the flash gate 45 and the gate electrode15 of the high voltage transistor HVTr are films having a high densityformed at high temperatures, thereby securing retention properties andintensity. Furthermore, in the memory transistor (Flash) and the highvoltage transistor HVTr, the second side walls 20M and 20H are disposedon the outside of the first side walls 10M and 10H, respectively. Inthis manner, the width of the entire side wall is controlled, such thatthe concentration profile of the source/drain extension of the highvoltage transistor HVTr is appropriately controlled. As a result, thesnapback withstand voltage is increased.

Specific embodiments of the present invention are described above.However, the present invention is not limited to the above describedexamples. From the above description, variations, alternatives, andmodifications may be apparent to those skilled in the art. For example,the width of the first side walls 10M and 10H may be appropriately setwithin a range of 75 nm through 85 nm. The width of the second sidewalls 20M, 20H, and 20L may be appropriately set within a range of 85 nmthrough 95 nm. In any case, the difference in the total side wall width(spacer width) between the high voltage transistor HVTr and the lowvoltage transistor LVTr corresponds to the width of the first side wall10H.

According to an embodiment of the present invention, in a mixed typesemiconductor device, the junction withstand voltage and the snapbackwithstand voltage on the drain side of a high-voltage operationtransistor HVTr are increased. Furthermore, the electric properties of alow voltage transistor LVTr are enhanced, and data saving properties ina memory transistor are ensured.

All examples and conditional language recited herein are intended forpedagogical purposes to aid the reader in understanding the inventionand the concepts contributed by the inventor to furthering the art, andare to be construed as being without limitation to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although the embodiments of the presentinvention have been described in detail, it should be understood thatthe various changes, substitutions, and alterations could be made heretowithout departing from the spirit and scope of the invention.

What is claimed is:
 1. A semiconductor device comprising: a firsttransistor including a first gate side wall insulating film and a secondgate side wall insulating film disposed outside of the first gate sidewall insulating film; a second transistor including a third gate sidewall insulating film that has the same composition as a composition ofthe first gate side wall insulating film, and a fourth gate side wallinsulating film that has the same composition as a composition of thesecond gate side wall insulating film, the fourth gate side wallinsulating film being disposed outside of the third gate side wallinsulating film; and a third transistor including a fifth gate side wallinsulating film that has the same composition as the composition of thesecond gate side wall insulating film and the fourth gate side wallinsulating film, wherein a total side wall spacer width of the thirdtransistor is smaller than a total side wall spacer width of the secondtransistor by a thickness corresponding to the third gate side wallinsulating film; wherein the first transistor is a flash memory; whereinthe second transistor is configured to operate at a higher voltage thanthe third transistor; wherein each of the first gate side wallinsulating film and the third gate side wall insulating film contains afirst silicon oxide film and a first silicon nitride film which isdisposed outside of the first silicon oxide film; wherein each of thesecond gate side wall insulating film, the fourth gate side wallinsulating film, and the fifth gate side wall insulating film contains asecond silicon oxide film and a second silicon nitride film which isdisposed outside of the second silicon oxide film; and wherein the firstsilicon oxide film has a higher density than the second silicon oxidefilm, and the first silicon nitride film has a higher density than thesecond silicon nitride film.
 2. A semiconductor device comprising: afirst transistor including a first gate side wall insulating film and asecond gate side wall insulating film disposed outside of the first gateside wall insulating film; a second transistor including a third gateside wall insulating film that has the same composition as a compositionof the first gate side wall insulating film, and a fourth gate side wallinsulating film that has the same composition as a composition of thesecond gate side wall insulating film, the fourth gate side wallinsulating film being disposed outside of the third gate side wallinsulating film; and a third transistor including a fifth gate side wallinsulating film that has the same composition as the composition of thesecond gate side wall insulating film and the fourth gate side wallinsulating film, wherein a total side wall spacer width of the thirdtransistor is smaller than a total side wall spacer width of the secondtransistor by a thickness corresponding to the third gate side wallinsulating film; wherein the first transistor is a flash memory; whereinthe second transistor is configured to operate at a higher voltage thanthe third transistor; wherein each of the second gate side wallinsulating film, the fourth gate side wall insulating film, and thefifth gate side wall insulating film is formed by a combination of aTEOS film and a nitride film; wherein the nitride film is disposedoutside of the TEOS film; wherein the nitride film covers the TEOS film;wherein each of the first gate side wall insulating film and the thirdgate side wall insulating film is formed by a combination of athermally-oxidized film and a nitride film.
 3. A semiconductor devicecomprising: a first transistor including a first gate insulating filmand a first gate side wall insulating film and a second gate side wallinsulating film disposed outside of the first gate side wall insulatingfilm; a second transistor including a second gate insulating film and athird gate side wall insulating film that has the same composition as acomposition of the first gate side wall insulating film, and a fourthgate side wall insulating film that has the same composition as acomposition of the second gate side wall insulating film, the fourthgate side wall insulating film being disposed outside of the third gateside wall insulating film; and a third transistor including a fifth gateside wall insulating film that has the same composition as thecomposition of the second gate side wall insulating film and the fourthgate side wall insulating film, wherein a total side wall spacer widthof the third transistor is smaller than a total side wall spacer widthof the second transistor by a thickness corresponding to the third gateside wall insulating film, wherein the first transistor is a flashmemory, wherein the second gate insulating film of the second transistorhas a film thickness that is larger than a film thickness of the firstgate insulating film of the first transistor, wherein each of the secondgate side wall insulating film, the fourth gate side wall insulatingfilm, and the fifth gate side wall insulating film is formed by acombination of a TEOS film and a nitride film, wherein the nitride filmis disposed outside of the TEOS film; and wherein the nitride filmcovers the TEOS film; wherein each of the first gate side wallinsulating film and the third gate side wall insulating film is formedby a combination of a thermally-oxidized film and a nitride film.